1. Field of the Invention
The present invention relates to a logic circuit design method, a computer-readable recording medium having a logic circuit design program stored therein, and a logic circuit design device, and particularly relates to a logic circuit design method, a computer-readable recording medium having a logic circuit design program stored therein, and a logic circuit design device that are applicable in logic circuit design using a hierarchical structure.
2. Description of the Related Art
As LSI circuits have become larger and larger in recent years, the use of design techniques such as so-called hierarchical division and tiling have become mainstream in physical design or layout design (i.e. operations for determining arrangement of cells and wiring between cells) of LSI circuits. It is therefore preferable in logical design, which is a preliminary process of physical design, to design a logical hierarchy corresponding to a physical hierarchy in view of convenience.
However, in some cases, logical design is made different from physical design because of CAD tool operability or designers convenience. For example, if a test circuit is inserted in a logic circuit in a DFT (Design For Test), a logical block to which the test circuit is inserted becomes different from a physical block (the term “block” used herein represents a level of hierarchy). Also, when designers input or verify logic circuits, they sometimes divide a hierarchy on a function basis for convenience reasons. In these cases, a hierarchy reconstruction operation is required after design operations so as to match a logical hierarchy to a physical hierarchy. Japanese Patent Laid-Open Publication No. 3-27474 (Reference 1) and Japanese Patent Laid-Open Publication No. 2003-256490 (Reference 2) disclose arts related to hierarchy reconstruction.
Reference 1 discloses a hierarchy reconstruction technique, in particular, a function that enables hierarchy reconstruction by moving instances between adjacent blocks, e.g., moving an instance X1 from a block B1 to an adjacent block B2 (see FIG. 1). However, it does not disclose a function for moving instances in other manners different from the manner described above with reference to FIG. 1 or a function for deleting hierarchical ports that have become unnecessary during a reconstruction operation.
Reference 2 also discloses a hierarchy reconstruction technique. This technique is applicable when two pins or ports are connected to a net, but it seems to be not applicable when three or more pins or ports are connected to a net.
Neither of these related arts discloses a function for assigning directions to newly created hierarchical ports, a method for processing a constant (if any) assigned to a pin of an instance to be moved or to a hierarchical port to be connected to the pin, and a technique for processing multiple instances that refer to the same module.
Because existing CAD tools only have limited functions for hierarchy reconstruction as described above, designers need to manually reconstruct hierarchy or perform complicated operations for hierarchy reconstruction using the existing CAD tools.